Erasure Coding – This is data coding added to a data set to enable a storage system to recover from the loss (erasure) of parts of the data set caused by, for example, a storage drive failure. A piece of data is split into sectors or chunks. These have codes generated from them and added to them with the now redundant data sectors stored across different drives. Should a drive fail the remaining data sectors, with the added erasure coded data, can be used to recover the lost (erased) data. 

Erasure coding requires less overhead (added redundant data codes) in general than a RAID data protection scheme. Erasure Coding schemes can be described as 4+2P (4 data and 2 parity), 4+3P, 8+2P, and 8+3P, etc.

ePMR – Enhanced Perpendicular Magnetic Recording. A Western Digital disk drive data recording technology which applies an electrical current to the main pole of the write head throughout the write operation, a bias current. This current generates an additional magnetic field which creates a preferred path for the magnetisation flip of media bits. This, in turn, produces a more consistent write signal, significantly reducing jitter.

The need for such a bias current is that disk recording heads can provide an inconsistent magnetic field to bits because their write currents can be distorted – so-called “jitter”. This effect makes bit value signal recognition more difficult and worsens as bits decrease in size and are placed closer together. 

Endurance – The working life of an SSD before its flash cells wear out. The wear out rate is related directly to the number of write cycles a cell has to endure. The smaller a flash cell is physically then the fewer electrons it contains to indicate its charge and hence bit value. The more bits per cell then the same relationship exists. That means that as flash cells become smaller and/or their bit count increases, their working life shortens. 

Here is an indicative table of representative raw endurance numbers for flash with different cell levels and different process sizes:

These are pre-3D NAND flash technology numbers. An SSD’s endurance can be extended by over-provisioning; having spare cells ready to be used to replace existing cells as they wear out.

Low-endurance flash can be used for read-centric applications such as archiving, where data, once written, is not changed.

BEOL – Back End of Line. The final stages of a semi-conductor process in which a wafer is built with component chips on it. ReRAM developers Intrinsic Semiconductor and Weebit Nano say their ReRAM technologies are BEOL-compatible and can be added to microcontroller semiconductor fabrication processes to provide embedded ReRAM memory on the microcontroller chips. This is an alternative to having a separately fabricated external memory module which would be more expensive and slower to access than on-chip memory.

Ei – Exbibyte or 1,024 pebibytes. See Decimal and Binary Prefix entry.

ECC – Error checking and Correction. ECC is a mechanism used to detect and correct errors in memory data due to environmental interference and physical defects. Most memory errors are single (1-bit) errors caused by soft errors (eg. cosmic rays, alpha rays, electromagnetic interference) but some can be due to hardware faults (eg. row hammer fault). Single bit errors can be corrected by ECC memory systems. Multi-bit errors, may also be detected and/or corrected, depending on the number of symbols in error.

ECC is implemented by generating and storing an encrypted, parity-like code used to not only identify the bit in error but correct it as well. This implementation-dependent ECC code is generated and stored on writes, and verified on reads. The most common implementations use Hamming codes for single-bit correction and double-bit detection. Hamming codes define parity bits which cover a pre-defined set of data bits. Typically, an 8-bit hamming code is used to protect 64-bit data. Hamming codes can detect one-bit and two-bit errors, or correct one-bit errors without detection of uncorrected errors.

ECC memory is a type of DRAM used in workstations and servers. ECC memory differs from non-ECC memory as it has nine memory chips instead of the usual eight, with the ninth chip being used for error detection and correction among the other eight memory chips.

EB – Exabyte – one thousand petabytes. See Decimal and Binary Prefix entry.

EAMR – Energy-Assisted Magnetic Recording – a disk drive recording technology in which energy, in the form of microwaves or heat, is applied to a magnetic recording medium which is resistant to having its polarity changed at room temperature. This is known as having high coercivity. The applied energy lowers the coercivity while the energy is applied, making it easier to write data to the medium, change its polarity in other words. Once the energy is withdrawn the coercivity returns to its previous high state and the polarity, and hence bit value, remains stable. See MAMR and HAMR.