The two have signed a Cooperative Research and Development Agreement (CRADA) to jointly explore developing efficient computing near storage, especially in settings where erasure encoding is needed for data protection. The two are collaborating on a proof-of-concept high-performance compute architecture that provides optimized computing capabilities across and within storage devices. It will allow for computing functions to be pushed down into an erasure-encoded HDD tier, providing faster, more efficient, less energy-intensive and less thermally demanding data retrieval.
A statement from Mike Moritzkat, CEO and managing director of Seagate Government Solutions, said: “The goal of this joint research is to optimize the efficiencies of a high-performance computing architecture by utilizing compute and memory resources of supporting storage systems down to the hard drive level. This in turn lowers overall TCO with full resource optimization.”
The erasure coding technique provides data protection and recoverability by breaking up data files or objects into multiple unrelated and distributed “chunks” of data across multiple drives. The scientific research at Los Alamos requires highly parallel disk drive technology that provides hundreds of petabytes of “warm” storage for large-scale simulations. That technology needs to be protected by two tiers of erasure coding, securing sensitive data against random and correlated failures.
This means that any computation on elements of the data set can need reconstitution of the data set – de-erasure coded so to speak – which requires time to read the data and host CPU cycles to retrieve the original data. This erasure coding makes it difficult to perform contextual computational operations and the Seagate-LANL collaboration aims to deal with this problem, down to having the disk drive processor run computations on the data inside the drive enclosure.
Ed Gage, VP of the Seagate Research Group, said: “Near data computing has always relied on knowing enough about the data to act accordingly; however, this architecture is the first known example of per-device computing that does not require re-constituting data into instances of the entire data set prior to exercising computing functions.
“This design allows for computing to occur on erasure-encoded data which is often present in hard disk drive storage architectures.”
Seagate and LANL intend to demonstrate that the potential of utilizing processing capability very near the disk devices can vastly reduce the amount of data that needs to be retrieved for the analysis part of a science campaign.
This will help speed processing during long simulations, such as tracking the very front of a shock wave traveling through a material or the state of only a few high energy particles across an extended simulation.
Gary Grider, HPC division leader at Los Alamos, said: “The promise of this work is to demonstrate measurably faster data query and retrieval using less energy and generating less heat. The other obvious goal is to provide this faster and lower power solution in a very economical way, making analytics of warm/cool disk-based data a more attractive solution for any large-scale erasure protected data be it on premise or in the cloud.”
In 2020, Seagate announced it had designed two processors based on the open RISC-V instruction set architecture (ISA). One, a high-performance variant, had been shown to be functional in hard disk drives.
Brad Settlemyer, LANL Senior Research Scientist, said: “At Los Alamos National Laboratory, using computational storage to move processing near data has begun to significantly alter the way we analyze data and perform scientific discovery.
“By having compute integrated closely with storage we are able to create persistent data transformations that speed up data analysis a thousandfold. This greatly relieves our primary compute tier from these tasks. We will be continuing our drive toward efficiency gains for our mission needs by partnering with vendors and actively participating in important industry initiatives like computational storage.”
John Morris, Seagate’s then CTO, said: “Introducing RISC-V to storage devices creates an opportunity to implement application-specific computational capabilities that enable massive parallel computational storage solutions. We believe that these architectures support many important use cases that include scientific simulation (for example, weather prediction) as well as the learning part of machine learning.”
It looks like this Seagate RISC-V processor work with LANL is developing nicely.
LANL is involved in computational SSD development work with SK hynix.