The OpenCAPI near memory CPU interconnect group plans to merge with CXL, paving the way to a single processor interface standard for near and far memory, and high-speed accelerator peripherals.
The not-for-profit Open Coherent Accelerator Processor Interface or OpenCAPI Consortium (OCC) was set up in 2016 by AMD, Google, IBM, Mellanox, and Micron to develop an alternative to the DDR channel to link memory to CPUs. There are several other members, including Xilinx and Samsung. Two other standards groups were set up which overlapped its aims: Gen Z and CXL (Computer eXpress Link). They merged in November last year.
Bob Szabo, OpenCAPI Consortium President, said: “We are pleased to see the industry coming together around one organization driving open innovation and leveraging the value OpenCAPI and Open Memory Interface provide for coherent interconnects and low latency, near memory interfaces. We expect this will yield the best business results for the industry as a whole and for the members of the consortia.”
OCC and CXL are entering an agreement, which if approved by all parties, would transfer the OpenCAPI and OMI specifications and OpenCAPI Consortium assets to the CXL Consortium.
OMI, the Open Memory Interface, is a CPU-to-memory bus that connects standard DDR DRAMs to a host CPU. It’s high-speed serial signalling “provides near-HBM bandwidth at larger capacities than are supported by DDR,” according to a white paper: The Future of Low-Latency Memory, co-authored by Objective Analysis (Jim Handy) and Coughlin Associates (Tom Coughlin) for the OpenCAPI consortium.
Siamak Tavallaei, CXL Consortium President, said: “Assignment of OCC assets will allow for CXL Consortium to freely utilize what OCC has already developed with OpenCAPI/OMI.”
CXL is now in pole position to oversee the development of a single standard for CPU to high-speed intelligent device linkage both inside and outside server chassis in racks.
The CXL consortium has a v3.0 specification coming, according to Design and Reuse. CXL v3.0 features:
- Fabric capabilities
- Multi-headed and Fabric Attached Devices
- Enhanced Fabric Management
- Composable disaggregated infrastructure
- Better scalability and improved resource utilization
- Enhanced memory pooling
- Multi-level switching
- New symmetric coherency capabilities
- Improved software capabilities
- Doubles the bandwidth to 64GTs
- Zero added latency over CXL 2.0
- Full backward compatibility with CXL 2.0, CXL 1.1, and CXL 1.0
Notably v3 adds symmetric coherency, which Jim Handy told us last month: “means that a single CPU manages the coherency of the whole system. Any limit on the CPU determines the maximum memory size that can be managed.”
Hopefully symmetric coherency will get round this single CPU coherency management problem and increase the total available memory capacity.
As CXL v3.0 is only just emerging into the light we might expect a future CXL 4.0 to include the OpenCAPI assets.
Comment
This is exceedingly good news, and clears the way for a single standard linking processors and intelligent fast accelerators and peripherals with memory, supported by all the manufacturers. It will encourage the formation of a single ecosystem with a wider market for the component manufacturers and a single overall focus for software developers.
