We have become so used to 3D NAND that we forget how revolutionary it was back in 2013. The idea that you could radically increase the density of a NAND wafer by stacking cells instead of just laying them out side by side is now taken for granted. We have 176-layer 3D NAND in production, 230-layer product coming, and 300-layers in development.
Update: Bootnote about Samsung interest in 3D DRAM added, 5 May 2023.
Yet DRAM is stuck fast in the planar era. It is fastened so solidly to 2D production technology that storage-class memories such as Intel’s Optane 3D XPoint were developed to provide near-DRAM speed but costs closer to NAND. Optane failed because its costs were kept high by limited production and the complexity of programming its non-volatile memory was too high.
Stacking DRAM cells is an obvious architectural approach to getting DRAM costs down and chip density up. Yet it is difficult and startup NEO Semiconductor believes it has found a way to do this with its 3D X-DRAM technology. Here we have a startup managing to create a 3D DRAM architecture before the main DRAM fabricators Micron, Samsung and SK hynix. NEO is a fabless operation and will need to have one or more of the three major DRAM foundry operators license its technology for it to succeed.
We asked memory semiconductor industry analyst Jim Handy of Objective Analysis how he viewed 3D DRAM technology.
He told us: ”The 3D NAND ‘Punch & Plug’ approach is well understood now, so a DRAM that uses this process should be able to ramp quickly, as long as it doesn’t use any new materials. Intel showed something similar in an 2020 IEDM paper. Tom Coughlin and I covered it briefly in our emerging memory report.
“The only drawback of the Intel approach is that it uses a doped HfO (hafnium oxide) antiferroelectric layer that’s not widely used in semiconductors. This renders it a little difficult to manufacture, simply because it’s not completely under the production floor’s control. I believe that it’s similar to the HfO that Germany’s Ferroelectric Memory Company (FMC) is working to develop into a production process. NaMLab at the University of Dresden discovered HfO’s ferroelectric properties in 2011, and the past 12 years its spin-off FMC has been spent trying to bring it under control. Things always look easy until you try to actually manufacture them!“
Intel of course is no longer in the memory business.
We asked Jim Handy a set of questions about NEO’s technology:
Blocks & Files: Do you have a public view of this technology and also of the company?
Jim Handy: NEO has been promoting a novel NAND flash concept at the Flash Memory Summit for a few years now. It uses the inherent capacitance of the bit lines as DRAM capacitors to vastly accelerate the performance of NAND flash. I’m not aware of any commercial product that has taken advantage of this technology yet. As for the DRAM technology, I only know what’s in the press release.
Blocks & Files: Is its claim to be able to have the technology progress to be capable of producing a 1Tbit DRAM chip in the be 2030-2035 period reasonable?
Jim Handy: As long as this is a production-worthy process that uses well-understood materials and a well-established 3D-NAND process, there’s no reason why a terabit DRAM could not be built sooner than that. If new materials are involved then the challenge of rendering them production-worthy would make that outlook much more difficult to predict.
Blocks & Files: If the 3D X-DRAM technology is viable, could it lead to a cost/bit reduction for DRAM in the same way as 3D NAND has helped lower the cost/bit for NAND?
Jim Handy: You bet! DRAM scaling has slowed significantly, and any low-cost breakthrough that would multiply DRAM density would accelerate DRAM’s slowing cost/bit declines.
Blocks & Files: Will 8x higher density DRAM chips overwhelm the x86 socket interfaces and be used more for HBM and CXL-accessed remote memory than server DIMMs?
Jim Handy: Computers can never have enough DRAM. If DRAM were free, and if its pin capacitance didn’t slow down the bus, then everyone would use considerably more than they use today. Instead, DRAM’s a costly thing to add, and the more chips/packages you add to any one channel, the slower you have to run that channel, so designers often limit themselves to only one or two DIMMs per channel.
In other words: cost is a limiter, and DRAM package count is a limiter. An 8x-denser DRAM would not only dramatically lower costs, but it would also support very large DRAM arrays with the same package count and capacitance that computers already deal with today.
One further advantage is that higher-density DRAMs provide more memory per watt. Datacenters have issues with DRAM’s power consumption and heat dissipation, so this would be a big plus for them as well.
Comment
NEO needs to find a memory fab operator that tests out the idea that 3D X-DRAM represents. In Handy’s words: “A production-worthy process that uses well-understood materials and a well-established 3D-NAND process.” Running an initial test shouldn’t take longer than a few weeks.
Intel’s experience with its doped HfO antiferroelectric layer shows how difficult it can be to get new materials into production. With 3D NAND, the flash foundry people had to step back to legacy cell technology, with physically larger cells, to bring it into production. Micron and the other DRAM producers are having to use smaller and smaller cells to increase DRAM wafer density. They could, we suppose, step back to legacy DRAM cell sizes to experiment with Neo’s 3D DRAM notion.
Let’s hope that this attempt at bringing 3D DRAM to production succeeds and we can all get the application speed benefits of x86 and GPU servers with much larger memory capacity.
Bootnote
Here is evidence of Samsung interest in 3D NAND with a paper from its researchers being presented at the 2023 Symposium on VLSI Technology and Circuits in Japan, June 11-16.
It’s entitled “Ongoing Evolution of DRAM Scaling via Third Dimension – Vertically Stacked DRAM. The papers abstract states: “For the past decades, the density of DRAM has been remarkably increased by making access transistors and capacitors smaller in size per unit area. However, shrinking devices far beyond the 10 nm process node increasingly poses process and reliability challenges. As Flash technology made a pivotal and successful innovation via 3D NAND, DRAM technology may also adopt vertical stacking memory cells. Vertically stacked DRAM (VS-DRAM) continues to increase bit density on a die by increasing the number of layers along with reducing the size of the transistor. In this paper, the opportunities and challenges of VS-DRAM are discussed.”
