SK hynix breezes past 300-layer 3D NAND mark

SK hynix engineers presented a paper at the ISSCC 2023 conference showing how they had developed a 300+ layer 3D NAND technology ingesting data at a record 194GBps speed. A copy of their paper shows how they did it using five techniques.

The paper is titled “High-Density Memories and High-Speed Interface” and was written by 35 SK hynix engineers. They write that “the most important topics for the NAND-Flash memory field are continuous performance improvements and cost/bit reduction. To reduce the cost/bit, the number of stacked layers needs to increase, while the pitch between stacked layers decreases. It is necessary to manage the increasing WL (wordline) resistance produced by a decreased stack pitch.”

They applied five new techniques to a >300-layer 1Tb 3b/cell (TLC) 3D-NAND flash memory product:

  1. A triple verify program (TPGM) technique is used to improve program performance. 
  2. An adaptive unselected string pre-charge (AUSP) technique is used to reduce disturb and program time (tPROG). 
  3. A programmed dummy string (PDS) technique is used to reduce WL settling time. 
  4. An all-pass rising (APR) technique is used to reduce the read time (tR), 
  5. A plane-level read retry (PLRR) technique is used during erase to improve the QoS.

The TPGM scheme reduces tPROG by narrowing the cell threshold voltage (VTH) distribution. SK hynix’s current double-verify program (DPGM) scheme divides cells into three groups while TPGM categorizes cells into four groups and so is better able to manage their program (write) performance. This “results in approximately a 10 percent of program time reduction,” the paper states.

The AUSP technique shortens program time by another 2 percent, we’re told. The PDS scheme contributes by reducing the capacitive load affecting the wordline’s settling time. The APR scheme reduces the wordline’s response time to a new voltage level, and improves read time by 2 percent.

The cumulative effect of these marginal and near-marginal gains is a 1 terabit 300+ layer TLC NAND cell with a 20Gb/mm2 bit density and a record 194GBps write speed, as a table indicates:

The paper also contains an image of the 300-layer die:

We’ve added this SK hynix 300-layer technology to our table comparing and contrasting supplier’s 3D NAND technologies:

Italicized entries are future generations. Will SK hynix subsidiary Solidigm use this 300-layer technology?

SK hynix (red oblong) is clearly in the lead in the 3D NAND layer count stakes. Product may appear, in our estimation, late this year or in 2024, and should enable SSDs with more capacity in less physical space.