Xilinx claims 10x CPU performance for Alveo FPGA

Xilinx has launched a FPGA that supports PCIe v4 and uses high-bandwidth memory to munch data manipulations faster and firehose the results.

Field-programable Gate Arrays (FPGAs) are reprogrammable hardware products used as CPU accelerators. Xilinx, founded in 1984, invented FPGA devices, also known as programmable logic devices.

The Alveo U50 follows on from existing U200 and U250 accelerators, which connect to host systems across PCIe v3  and use DRAM memory.

The half-height, half length device delivers a claimed 10-20x improvement in throughput, latency and power efficiency, with a 75-Watt power envelope.

It has 8GB of high-bandwidth memory (HBM2) with greater than 400 Gbit/s data transfer speed, and 100Gbit/s external connectivity. That helps support for NVMe-over-Fabrics and disaggregated computational storage – a hint about composable systems.

It also supports CCIX, the Cache Coherent Interconnect for Accelerators

Target application areas are deep learning inference, data analytics, computational storage, network acceleration and financial modelling.

For data analytics, Xilinx claims the U50 provides 4x higher throughput per hour and reduced operational costs by 3x compared to in-memory Xeon Platinum 8260 CPU, with a 24ms query time compared to the Xeon’s 210ms.

Xilinx is showcasing the Alveo U50 at the Flash Memory Summit 2019, August 6-8 at Santa Clara.

The Alveo U50 is sampling now with OEM system qualifications in process. General availability is slated for Fall 2019.

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