A Stanford University team is researching gain cell memory, combining SRAM and DRAM features, to speed GPU memory data access, validating Israeli startup RAAAM Memory Technologies‘ system-on-chip (SoC) development.
Gain cells use an additional transistor to amplify memory cell read signals and boost data access compared to DRAM. The research team, led by H.-S. Philip Wong, a Stanford Professor of Electrical Engineering, says there is a memory wall problem with a GPU’s on-chip and fast, expensive SRAM having to be loaded with data from a server’s comparatively slow main memory (DRAM). This takes too much time and electrical energy, and it would be better if the two memory types could be combined or SRAM replaced by something better.
An SRAM (static random access memory) cell is quite large in area, needing four transistors to store a bit and two to control access to the cell. The ability to reduce the size of SRAM cells is running out, limiting SRAM chip capacity increases.
DRAM cells are simpler and smaller. They need a single transistor, a source with a bit line connection, a gate with a word line connection, a capacitor to store charge, and a drain; a 1T1C architecture. They are volatile, needing constant refreshing of their bit state, and suffer from destructive reads with their bit state having to be re-established after every read.
Embedded DRAM (eDRAM) could be placed on the GPU system-on-chip (SoC) and so increase capacity, but Wong’s team says its capacitor process has incompatible logic. We need on-chip memory that combines SRAM speed and DRAM capacity, which can be done by having DRAM-like cells with separate read and write (storage) transistors. No extra capacitor is needed because this design amplifies the read signal.
Wong’s team devised a twin oxide silicon (OS-OS) gain cell, but then developed a hybrid gain cell in which the two transistors are made from different materials, as having two silicon oxide-based transistors slows bit-state signal reading.
Wong’s team developed an ALD ITO (atomic layer deposition indium tin oxide) FET write transistor with a Si PMOS (silicon P-channel metal-oxide-semiconductor) read transistor. A scientific paper on the subject published by the IEEE can be found here (subscription required). According to research results presented at the IEEE Symposium on VLSI Technology and Circuits in June, the gain cell device retains data (its bit state) for more than an hour (>5,000 seconds) contrasting with DRAM’s need to be refreshed every 64 ms, and data is read up to 50x faster than from a OS-OS transistor gain cell, with a 1-10 ns access time:
Also, PMOS transistors consume very little power when in the off state. Gain cell reads are non-destructive and preliminary results show them being fairly close to DRAM in several characteristics:
RAAAM says its GCRAM (gain-cell random access memory) technology can be used as a drop-in SRAM replacement in any SoC, allowing for lower fabrication costs through reduced die size or enhanced system performance by increasing memory capacity within the same die size. Its technology is described in a downloadable slide deck.
In essence, both GCRAM and the Wong team’s hybrid gain cell memory are intended to replace SRAM rather than DRAM, with a higher capacity gain cell memory being slower than SRAM in some performance aspects. But it makes up for that by having a much higher capacity, so reducing the existing SRAM-to-DRAM data transfer traffic and thus increasing overall system performance.
Potential customers are producers of processor SoCs for GPUs and CPUs in datacenters and also embedded systems.
