SoftIron plants FPGA in network card to speed Ceph workloads

SoftIron has introduced the Accepherator, an FPGA accelerator that speeds up erasure coding for Ceph storage workloads.

This saves host CPU cycles for application work and reduces storage capacity requirements.

Ceph provides file, block and object storage from the same distributed storage pool and ensures data reliability by keeping three copies (replicas) of the data spread across many drives. This keeps data available if a drive fails but uses three times more storage as a single copy of the base data.

Erasure coding splits data into chunks, added parity bits to each chunk, and requires less overhead – 1.33 times the original data in Softiron’s scheme. If a drive fails the parity bits on remaining chunks are used to rebuild the lost data. The upshot is less storage capacity for the same data.

Normally a host CPU computes erasure coding parity bits and this can slow storage writes. SoftIron has programmed an FPGA to do this work and put it inside a 10GbitE SFP network interface card.

Accepherator NIC with FPGA for erasure coding

SoftIron CTO Phil Straw said: “We’ve managed to cut the overall total cost of ownership in half by virtue of the fact you now only require 1.33x replication, and you don’t need expensive CP’s for the erasure coding.”

The Accepherator is on sale as an option for SoftIron’s HyperDrive Ceph storage products.