UCIe – Universal Chiplet Interconnect Express. This is an open semiconductor-level specification for a die-to-die interconnect and serial bus between chiplets; small chips. it is a way to avoid building bigger and ever more complex large chips by breaking them up into smaller chip-level components; chiplets, which can be connected together in System-on-Chip (SoC) packages. The component chiplets can be made with different process geometries and by different vendors. UCIe was co-developed by AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, Samsung and TSMC.
The UCIe 1.0 specification was released on March 2, 2022 defining a physical layer, protocol stack and software model, and procedures for compliance testing. The physical layer supports up to 32 GT/s with 16 to 64 lanes and uses a 256 byte FLIT (Flow Control Unit) for data. This is similar to PCIe gen 6, and protocol layer is based on CXL (Compute Express Link) with CXL.io (PCIe), CXL.mem and CXL.cache protocols.