ULTRARAM: potential new storage-class memory from the UK

Researchers at the UK’s Lancaster University say they have devised a new ULTRARAM non-volatile memory combining DRAM speed and flash endurance. A spinout company is being setup to try to commercialize it.

Professor Manus Hayne, ULTRARAM inventor
Professor Manus Hayne

Physics professor Manus Hayne led the team that invented ULTRARAM, a charge-based memory where the logic state is determined by the presence or absence of electrons in a floating gate. This technology depends upon quantum resonant tunneling in compound semiconductors. Each cell has a floating gate accessed through a triple-barrier resonant tunneling heterostructure. 

The Lancaster Uni team says compound semiconductors are commonly used in photonic devices such as LEDs, laser diodes and infrared detectors, but not in digital electronics, which uses silicon semiconductors. But ULTRARAM can be built on a silicon substrate. A research paper says: “Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers.”

III-V refers to a compound semiconductor alloy, containing elements from groups III and V in the periodic table, such as Gallium Arsenide.

The paper’s abstract says: “Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10 ms duration program/erase pulses of ≈2.5 V, a remarkably fast switching speed for 10 and 20 µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.”

The researchers contrast DRAM and NAND: “A fast, high-endurance memory seemingly necessitates a frail logic state that is easily lost, even requiring constant refreshing, for example … DRAM. In contrast, a robust, nonvolatile logic state ostensibly requires large amounts of energy to switch, which (gradually) damages the memory structure, reducing endurance; for example, flash.”

Resistive RAM, magnetoresitive RAM, and phase-change memory technologies are subject areas of R&D trying to bridge these two states. They say: “ULTRARAM breaks this paradigm via the exploitation of InAs (Indium arsenide) quantum wells (QWs) and AlSb (Aluminium antimonide) barriers to create a triple-barrier resonant-tunneling (TBRT) structure … By using the TBRT heterostructure as the barrier between FG and channel, rather than the usual monolithic material, a charge-based memory with extraordinary properties can be achieved.”

A quantum well is a region in a three-dimensional structure in which particles are forced to occupy a two-dimensional region in which they have discrete energy values. Quantum well devices operate very quickly, need little electricity, and are used in photonic devices. AISb is a semiconductor.

ULTRARAM device concept
ULTRARAM device concept. a) Schematic cross-section of a device with corresponding material layers. The floating gate (FG), triple-barrier resonant-tunneling structure (TBRT), and readout channel are highlighted. Arrows indicate the direction of electron flow during program/erase operations. b) Scanning electron micrograph of a fabricated device of 10 µm gate length. c, d) Nonequilibrium Green’s functions (NEGF) calculations of density of states alongside conduction band diagrams for no applied bias (i.e., retention) and program-cycle bias respectively. B1, B2, and B3 are the AlSb barrier layers. QW1 and QW2 are the InAs quantum wells in the TBRT.

The abstract says: “The 2.1 eV conduction band offset of AlSb with respect to the InAs that forms the floating gate (FG) and channel, provides a barrier to the passage of electrons that is comparable to the SiO2 dielectric used in flash. However, inclusion of two InAs quantum wells (of different thicknesses) within the TBRT structure … allows it to become transparent to electrons when a low voltage (≈2.5 V) is applied, due to resonant tunneling.” SiO2 is Silicon Dioxide.

The charge state of the floating and, therefore, the logic state of the memory, is read non-destructively by measuring the current through the channel when a voltage is applied between the source (S) and drain (D) contacts.

Here’s the kicker: “Due to the low voltages required and the low capacitance per unit area of the device compared to DRAM, ultralow logic state switching energies of 10−17 J are predicted for 20 nm feature size ULTRARAM memories, which is two and three orders of magnitude lower than DRAM and flash respectively.”

They conclude: “Testing of the fabricated single cell memory devices shows strong potential, with devices demonstrating a clear memory window during ≤10 ms program/erase operations, which is remarkably fast for 10 and 20 µm gate-length devices. The ≈2.5 V program/erase voltage and low device-areal-capacitance results in a switching energy per unit area that is 100 and 1000 times lower than DRAM and flash respectively. Extrapolated retention times in excess of 1000 years and degradation-free endurance tests of over 107 program-erase cycles prove that these memories are nonvolatile and have high endurance.” 

If this can be commercialized and fabricated at an attractive cost then we have a new storage-class memory. The technology has already been patented in the US and spinout discussions are taking place with potential investors.