Kioxia and WD’s BiCS 8 tech takes YMTC route: Separately fabs NAND control logic and cell stacks

Kioxia and Western Digital have devised 218-layer 3D NAND technology with separately fabricated control logic and NAND cell dies bonded together.

Traditionally the control logic and cell logic are fabricated monolithically on one wafer. SK hynix calls its version of this fabrication Peri Under Cell (PUC) while WD and Kioxia have referred to it as CUA (Circuit Under Array). YMTC has had a different and, until now, unique, Xtacking design, in which the peripheral logic circuitry was fabricated separately from the NAND cells and bonded to the top of the NAND cell stack. This enabled it to have more freedom in developing the control logic circuitry. Now Kioxia and WD have followed suit with what they call their BiCS 8 technology.

Kioxia CTO Masaki Momodomi said in a statement: “Through our unique engineering partnership, we have successfully launched the eighth-generation BiCS FLASH with the industry’s highest bit density. I am pleased that Kioxia’s sample shipments for limited customers have started.”

WD SVP of Technology & Strategy Alper Ilkbahar added: “By working with one common R&D roadmap and continued investment in R&D, we have been able to productize this fundamental technology ahead of schedule and deliver high-performance, capital-efficient solutions.”

The BICs 8 layer count of 218 looks slightly underwhelming compared to SK hynix’s 238-layers, Samsung’s 238-layer NAND, Micron’s 232-layer technology and YMTC’s 232 Xtacking layer count.

B&F NAND suppliers’ layer count generations table

Kioxia and WD claim they can get increased cell density in their 218-layer chips because they shrink the cells both laterally and vertically. They say this produces greater capacity in a smaller die with fewer layers at an optimized cost. 

The 238-layer chips have 1 terabit capacity with either TLC (3bits/cell) or QLC (4bits/cell) formatting. The chip’s IO rate is 3.2Gbps, 60 percent more than prior BiCS 6 chip’s 162-layer NAND. There is also a a 20 percent write performance improvement and lower read latency compared to BiCS 6 technology. 

An intervening BiCS 7 technology was abandoned by Kioxa and WD, with the CUA development and cell shrinkage enabling BiCS 8.

We might expect to see SSDs using BiCS 8 technology in a quarter or two.

TL:DR summary: Kioxia and WD say it’s not just the layer count that matters but the cell density size and layer count together. This way they get more bits in a smaller more cost-effective chip than their layer-count focused competitors, they claim.


Neither Kioxia nor WD have issued any imagery or diagrams illustrating their BiCS 8 technology. Neither did Kioxia CTO Liu Maozhi discuss BiCS 8 at the 2023 China Flash Memory Summit.