Kioxia NAND researchers say they have proven that Hepta Level Cell NAND with 7 bits per cell is a workable possibility.
After demonstrating 6-bit hexa-level cell flash in August 2021 using NAND cooled to the boiling point of liquid nitrogen (77 K or -196° C) the researchers have upped their game by one more bit, inventing a cell with 128 voltage states.
- SLC – 1 bit/cell – 2 voltage (Vth) states
- MLC – 2 bits/cell – 4 states
- TLC – 3 bits/cell – 8 states
- QLC – 4 bits/cell – 16 states
- PLC – 5 bits/cell – 32 states
- HLC – 6 bits/cell – 64 states
- ? – 7 bits/cell – 128 states
Cryogenic cooling worked for 6-bit cells but more was needed for 7-bit ones. They combined the same cryogenic cooling with new silicon process technology to improve cell readability.
Existing NAND uses poly-silicon for the channel in a memory cell transistor. The read process detects the bit value of the cell by determining the threshold voltage (Vth). As the number of bit levels increase the amount of read noise increases too, blurring the read signal. The poly-silicon was replaced by the Kioxia researchers with single-crystal silicon, grown epitaxially, which reduces the read noise by two thirds compared to poly-silicon.
If such 7 bits/cell NAND has acceptable endurance then it might make it into production. This could have a significantly lower bit cost, the researchers say, taking the cryogenic cooling into account. Getting the technology to work at room temperature would be the big win.
Japanese startup Floadia is also working on 7-bits/cell technology but applied to AI with a SONOS (silicon–oxide–nitride–oxide–silicon) architecture Compute-in-Memory chip. This stores neural network weights in non-volatile memory and executes a large number of multiply-accumulate calculations in parallel by passing current through the memory array. It is aimed at microcontrollers in edge locations.
The Kioxia researchers have inadvertently created an acronym problem as the HLC (Hexa-Level Cell) term was used by them for the 6 bits/cell tech, and 7-bits/cell would logically be Hepta-Level Cell, also HLC. Oops.
Septi-Level Cell is out, because we already have SLC, as in Single Level Cell. Oh dear.
We have to confess to a degree of tardiness here as we have only just discovered the Kioxia paper:
H. Tanaka, Y. Aiba, T. Maeda, K. Ota, Y. Higashi, K. Sawa, F. Kikushima, M. Miura, and T. Sanuki, “Toward 7 Bits per Cell: Synergistic Improvement of 3D Flash Memory by Combination of Single-crystal Channel and Cryogenic Operation,” 2022 IEEE International Memory Workshop (IMW), 2022, pp. 1-4
It was presented at the International Memory Workshop (IMW) in May 2022 and you have to negotiate a paywall to read the text.