Startup Neo Semiconductor previously introduced X-NAND technology, which carves a NAND die into multiple parallel planes to speed IO. Now it says it has launched a second generation to speed it up twice as much again.
The technology takes a base NAND die with two to four access planes. Each plane is divided into four to 16 sub-planes, each accessed in parallel. Page buffers are used to optimize data throughput speeds. A brochure explains that with gen 1, a total of four planes are used for SLC/TLC parallel programming. Input data is programmed into three SLC word lines in three planes and then programmed to a TLC word line in a fourth plane.
This enables a gen 1 X-NAND SSD to deliver 1,600 MB/sec of sequential write throughput compared to the basic SSD’s 160MB/sec.
Gen 2 X-NAND does things differently. Two planes are used for SLC/TLC parallel programming. Input data is programmed into three SLC word lines, as before, but now only in one plane, and then programmed to a TLC word line in a second plane. This enables data writes to occur in parallel with fewer planes, and X-NAND delivers SLC-like performance from larger capacity and lower cost QLC memory.
X-NAND gen 2, says Neo Semiconductor, delivers 3,200MB/sec of sequential write throughput, 20x faster than a basic SSD. There are also unspecified latency improvements.
It also provides 3x the base random read/write speed and there is zero increase in die size.
X-NAND architecture supports SLC, MLC, TLC, QLC and PLC variants of NAND. The IP can be deployed by NAND manufacturers (Kioxia, Micron, Samsung, SK hynix, Solidigm, Western Digital, and YMTC), and is compatible with current technologies and processes with zero increase in manufacturing cost. At least this is the pitch by Neo Semiconductor.
The technology was awarded a “Best of Show” award for the Most Innovative Memory Technology at FMS 2022. So far we have not heard of any NAND manufacturers using Neo’s X-NAND technology. Find out more about it here.
Neo Semiconductor also has an X-DRAM technology, based on shorter bit lines and reduced capacitance, which adds parallelism. This, it says, increases DRAM performance with 400 percent refresh data throughput, lowers the voltage needed, and reduces overall power consumption.