Brains behind Intrinsic Semiconductor Technology on ramifications of ReRAM

Intrinsic Semiconductor Technology is raising money to fund a foundry for its ReRAM chip and to build a memory compiler so microcontroller makers can replace SRAM with cheaper, simpler ReRAM. We first encountered Intrinsic and its ReRAM last month. ReRAM or resistive RAM is a type of memristor, according to Intrinsic CEO Mark Dickinson, and is non-volatile, faster than DRAM, and as fast as SRAM (Static Random Access Memory). 

Mark Dickinson

Blocks & Files was briefed by Dickinson and Intrinsic co-founder Dr Adnan Mehonic, a research scientist at University College of London (UCL). Mehonic’s full title is Assistant Professor in Nanoelectronics & RAEng Research Fellow at UCL and CTO at Intrinsic. The underlying technology was described in our February article and this briefing detailed many other attributes of their ReRAM and the steps needed for a user wanting to adopt their technology.

The most important basic parameter here is access speed as that positions the various memory technologies in a hierarchy. As a remidner and for reference, 1ms (millisecond) equals 1,000μs (microseconds) and 1μs equals 1,000ns (nanoseconds). To set the scene we’ll lay out the speeds of HDDs, NAND, DRAM, NOR, SRAM and ReRAM, starting with HDDs (Hard Disk Drives), which have a rough 10ms data access time. Next is NAND flash, with a general 70 to 87μs read time for TLC (3bits/cell) and an approximate 15μs write latency.

Next we have DRAM, which has speeds of 60-100ns and also higher bandwidth as 128 or 256 bits might be fetched in a single access. NOR flash is faster than DRAM with a 50-76ns (Micron Xccela NOR) read latency. Then speeds become higher still, with SRAM read latency in the 1-10ns area. ReRAM speed is the same as SRAM and rated as storage-class memory because it is non-volatile.

Dr Adnan Mehonic

Intrinsic says that ReRAM is simpler to make than NAND, with only two or three different layers needed compared to the 20 to 30 required to make a NAND die. Mehonic told us: “These are 2-terminal devices, having a capacitor-like structure rather than a 3-terminal transistor. It’s very much simpler.” ReRAM dies are smaller than equivalent capacity NAND dies because of this.

SRAM cells are more complex than ReRAM cells, needing 4 or 6 transistors or even more.

To our surprise, Intrinsic’s ReRAM can have multi-bit cells, like NAND, but using resistance levels rather than voltage levels, as ReRAM is passive. We asked Mehonic how many bits (resistance levels) there could be in a ReRAM cell, and he said: “32 or 64. It could be even more.” 

There is a lot of headroom between the lowest level of ReRAM resistance and the maximum level, and that spectrum of low to high resistance can be subdivided into 32, 64 or possibly even more divisions which can, in theory, be accurately read. And read more easily than testing the voltage level in a multi-bit NAND cell.

Dickinson and Mehonic emphasised their core expertise was knowledge of what happens in the thin silicon dioxide layer in ReRAM and how to engineer or control the composition of the material to get the right oxygen filament formation and deformation characteristics in a predictable fashion. Mehonic talked about micro-engineering the oxide layer and said: “We have a deep understanding of the physics of the material.”


The pair told us SRAM is a replacement candidate because, although SRAM can be embedded into a microcontroller unit (MCU), unlike NAND, writing to SRAM is costly in a power sense. SRAM is also volatile, only holding data as long as power is applied. MCU builders could have more embedded memory capacity through using ReRAM than by using SRAM because ReRAM cells are smaller and need less power to operate.

When a MCU is woken up from sleep mode, data and possibly code is read in from external memory, NAND or NOR, and loaded into SRAM.  Were the MCU to be built with ReRAM instead of SRAM, the data and code would already be in ReRAM, and not need to be loaded from an external memory. We would have instant-on from sleep mode and instant boot. 

The MCU embedded memory market, with memory as part of the die,  is worth around $20bn, according to Dickinson. Once Intrinsic has an embedded memory business, it will look at the external memory market and possibly expand into that.

Memory compiler

The customers of Intrinsic’s technology will be firms making MCUs to do some specific task and needing embedded memory to store data and software. Currently that will be either an external NAND chip – external because it cannot be fabbed in the same process that makes the MCU – or an SRAM feature. 

MCU makers will need to be convinced that Intrinsic’s ReRAM is real and can be built in the same process as an MCU. In effect, layers are added to the MCU die to provide the ReRAM capacity and functions. The best way to convince potential customers that this can be done is to do it, using an example MCU with Intrinsic acting as the semiconductor fab client.

The ReRAM is added to the MCU by using a memory compiler. The ReRAM design is fed into the memory compiler, which processes it to produce a set of configuration instructions that the fab can use to add ReRAM layers to the MCU. Intrinsic can then take the working MCU-ReRAM chip plus memory compiler to potential customers and show them what to do in order to add ReRAM to their own MCUs.

Dickinson said: “We’re raising our next round of funding now, and hope to make an announcement in the not too distant future.”