Marvell has launched a flash controller using the PCIe gen 5.0 bus, four times faster than today’s mainstream PCIe gen 3 bus.
PCIe v3 operates at 8 gigatransfers/sec, translating to an aggregate of 32GB/sec across 16 lanes. PCIe v4 doubles that to 64GB/sec and PCIe v5 doubles that again to 128GB/sec. Marvell’s Bravera SC5 SSD controller is the world’s first PCIe v5.0 controller and comes with either 8 or 16 NAND channels. It delivers up to 14GB/s sequential read bandwidth and 1.8 million random read IOPS.
Marvell said it worked with hyperscale users, such as Azure and Facebook, in developing the new controller. Facebook storage hardware systems engineer Ross Stenfort supplied a quote: “There are many data centre technology challenges. These include the need for PCIe 5.0 for performance scaling, E1.S for density and serviceability and OCP data centre NVMe SSD support for product features. Marvell’s Bravera SC5 SSD controller family supports technology that enables next generation hyperscale SSD use cases.”
There are several other Bravera launch partners, including Kioxia, SK hynix, AMD and Intel. According to Marvell the Bravera controllers are poised to be the foundation for data centres that offer ultra-low latency, real-time applications while also providing cost-optimised and cloud-scale capacity.
The Bravera controller supports SLC, TLC and QLC (4bits/cell) flash, the Open Compute Project (OCP), new ruler formats such as E1.S, E1.L and E3, software-enabled flash, zoned namespaces, Open Channel, and NVMe 1.4b. Its latency is less than 6μs and it supports 4 PCIe v5 lanes or, in dual-port mode, 2 lanes. Marvell has said it has a hardware-based elastic SLA (service level agreement) enforcer.
From the security point of view, Bravera offers FIPS-compliant root of trust (RoT), AES 256-bit encryption and multi-key revocation.
The Bravera controller is sampling now with prospective customers.