NAND inventor’s company invents Dynamic Flash Memory – a theoretical DRAM replacement

A company set up by NAND inventor Dr Fujio Masuoka claims to have devised DRAM replacement technology called Dynamic Flash Memory (DFM), with flash-like block refresh and erase.

A DFM paper, “Dynamic Flash Memory with Dual Gate Surrounding Gate Transistor (SGT)”, was presented at the 13th IEEE International Memory Workshop (IMW) on 18 May by its co-inventors, doctors Koji Sakui and Nozomu Harada from Unisantis Electronics of Singapore. Masuoka, born in 1943, set up Unisantis in 2008 to develop the vertical Surround Gate Transistor (SGT) technology which is used in DFM. There are more than 700 Unisantis patents covering SGT and its potential uses cases include SRAM, DRAM, MRAM, RRAM/RERAM, logic circuits, and CMOS image sensors.

In a Unisantis announcement, Dr Koji Sakui said: “The memory industry has long-since accepted DRAM technology is nearing the end of its life, but its significant market means any replacement technologies must provide the right balance of performance, costs and future scalability. After significant internal research and testing, we are delighted to unveil DFM to the market as the leading long-term viable option to DRAM.”

A DRAM cell typically stores electrical charge in a capacitor. They have to be large enough to store a measurable charge and, as they leak charge, need periodical refreshing, which is why they are volatile; not holding their contents – the charge – when power is turned off. The charge is also destroyed when a cell is read, necessitating sense amplifiers per memory cell row, to temporarily hold cell data on a read, and a write cycle to refresh the cell.

The Unisantis paper says DFM takes a revolutionary approach to overcome these DRAM limitations short, regular and power-hungry refresh cycles, as well as destructive read processes.

Unisantis states: “Unlike the so-called ‘emerging memory technologies’ (MRAM, ReRAM, FRAM, PCM) DFM does not involve adding additional materials on top of a standard CMOS process – an approach that drives up the cost, prohibitively.”

The SGT technology uses a 3D pillar structure, orienting a field-effect transistor (FET) in a vertical direction: 

Unisantis FET Surround Gate Transistor.  (a) cross-section drawing of an n-channel SGT.  (b) Electron microscopy of fabricated SFT. This topology is also referred to in the semiconductor industry as a vertical nanowire transistor.

 The gate, which completely surrounds the silicon pillar channel, is the PL gate in the next Unisantis diagram:

Partial key; BL = bit line. WL = word line. PL = plate line. SL = source line.

Unisantis says  the vertical SGT offers several benefits in a circuit implementation:

  • Improved areal density, compared to planar and FinFET transistors
  • Reduced leakage power, due to the strong electrostatic control of the surrounding gate to the transistor channel
  • Optimisation of the transistor width and length dimensions for the end application, whether high-performance or extremely low power dissipation

A third Unisantis diagram casts more light on the SGT design:

The DFM/SGT technology still leaks charge but at a much slower rate than DRAM, and reads are non-destructive. That means the interval between refresh cycles is longer and there is therefore more read and write bandwidth. DFM/SGT provides block refresh and erase, and also provides faster access speed than DRAM.

Unisantis claims DFM has a substantial potential, in simulation at least, to have four-times the density of DRAM, with significant Gb/mm2 improvements.  It says today’s limits on DRAM (currently 16Gb) could immediately see increases to 64Gb memory using DFM’s cell structure.

Unisantis has developed its DFM concept and is now looking to develop a series of memory and foundry partnerships to publicly test and demonstrate the features and potential of DFM. There are private discussions taking place with potential partners, we’re told. Meanwhile it will continue with its internal DFM development.