In our recent interview with Siva Sivaram, the Western Digital’s president for technology and strategy discussed upcoming solid state storage technology. Let’s begin with his thoughts on storage-class memory.
Storage-class memory (SCM) is faster than NAND but slower than DRAM. It slots between the two in the memory-storage hierarchy and there are a number of candidate technologies vying to become the SCM leader; PCM, MRAM, FeRAM, STT-RAM and others.
Some analysts suggest storage-class memory (SCM) could ultimately replace NAND and – if fast enough – DRAM, to become a universal memory.
Sivaram doesn’t buy into this notion. No universal SCM technology will supplant NAND and DRAM, he argued. “The future for NAND is NAND. The future for DRAM is DRAM,” he said. “There is no general storage-class memory market.”
According to Sivaram, SCM is a collection of specialised niches, with “different types for different applications.” For instance, MRAM is suited to a certain niche market while FERAM is suited to another.
WD has looked at many different types of SCM technology over the years, such as PCM, MRAM and FeRAM. “We have done a lot of work on it. We hold the original patents on XPoint and 3D XPoint. We built 8-layer crosspoint in 2004 [and] we’re watching the area closely.”
To emphasis WD’s involvement with SCM, Sivaram said Western Digital even made $400m from shipping certain SCM products in 2004.
QLC flash adoption
Each flash technology level change goes undergoes improvements in performance, endurance and reliability (PER). At any layer count transition point, such as 64-layer to 96-layer, it is feasible to move to the extra bits/cell generation, for example, from MLC (2bits/cell) to TLC (3 bits/cell).
Sivaram said: “TLC gets better generation to generation. But this runs out. So QLC becomes more interesting.” For Western Digital, cost-benefit considerations about cell bit count increases are based on first deciding if PER improvements achieved from the extra layers are enough to meet market demand. If not, should WD also increase the cell bit count? This gives extra capacity but at the cost of lowering the PER value of the increased layer count.
Controller advances and over-provisioning can mitigate the disadvantages of the cell bit count change.
That is happening now with QLC flash, Sivaram said. Enterprise SSDs using 3D NAND with 96 layers are best with TLC cells. But the next layer generation, known as 1xx – 100-plus layers – will likely be QLC flash.
As an aside, Sivaram mentioned that 3D NAND has dummy layers with no bits in them – it is just a feature of the way 3D NAND is made. He said a strict layer count, including the dummy layers, would turn a 96-layer 3D NAND die into a 100+ layer one. However, WD only counts layers with wordlines, meaning shippable bits in them, and ignores the dummy layers.
The implication is that other manufacturers may not do this and one manufacturer’s 112 layers, for example may not be the same as another manufacturer’s 112 layers. This makes layer-count based comparisons between suppliers more difficult.
Penta-level cell flash
Penta-level cell flash (5bits/cell or PLC) means selecting one of 32 voltage levels in a cell. This takes longer than the 16 voltage levels of QLC flash and read performance is slower and longevity is worse than QLC flash.
PLC delivers more capacity but raw PER values are all lower than QLC flash. Sivaram believes PLC adoption will take place in the next two to three years because of the diminishing returns from QLC generational advances. By then, “controllers will have machine learning algorithms” and will be better able to manage PLC flash’s limitations, he said.
The transition from QLC to PLC will follow the same pattern as the MLC-TLC and TLC-QLC transitions. It’s a feature of the industry, according to Sivaram.
N.B. Read our interview with Siva Sivaram, concerning enterprise disk drive technology, here.